Method and apparatus for measuring a low power signal

ABSTRACT

When low intensity light ( 4 ) is incident upon a photodiode ( 2 ), the output from the photodiode ( 2 ) is coupled to an integrator formed by an operational amplifier ( 7 ), a capacitor ( 8 ) and a FET coupled in parallel in a feedback path between an output ( 9 ) of the operational amplifier ( 7 ) and its negative input ( 5 ). The output ( 9 ) of the operational amplifier ( 7 ) is coupled to an input of an A/D converter ( 21 ), whose output is coupled to a microprocessor ( 22 ), whose output is coupled to a filter ( 23 ). A second output of the microprocessor ( 22 ) is coupled to a gate electrode of FET  10  to provide a reset signal to the FET  10  to reset the integrator. The microprocessor ( 22 ) compares the digital samples of the integrated signal from the A/D converter and, firstly, generates the reset signal if a sample is beyond a set limit, and, secondly, calculates delta values between adjacent samples and interpolates the delta values for the reset periods so as to provide a continuous data stream which can be filtered by a filter matched to the form of the original signal.

DESCRIPTION

[0001] 1. Field of the Invention

[0002] This invention relates, in general, to a method and apparatus formeasuring a low power signal, and more particularly to a method andapparatus for measuring a low power signal based on a low light signal,for example a low light signal from a photo diode.

[0003] 2. Background of the Invention

[0004] In many systems, a light receiving device, such as a photo diode,photo avalanche diode or photomultiplier tube, emits an electric signalbased on the amount of light (number of light photons) incident on alight sensitive portion of the light receiving device. In order to thenprovide a useful signal providing an indication of the amount of lightincident on the device, the electric signal from the device isintegrated over predetermined time periods, filtered, converted to adigital signal and then suitably processed.

[0005] One known way of carrying out this processing is known from U.S.Pat. No. 5,959,291 (Jensen) in which a photodiode is coupled acrosspositive and negative input terminals of an operational amplifier, thepositive input terminal of the operational amplifier being coupled toground and a capacitor and a field effect transistor being coupled, inparallel, between the negative input terminal and the output of theoperational amplifier, the gate of the transistor serving as a resetsignal. The output of the operational amplifier is coupled to the inputof a low-pass filter, whose output is coupled to an input of ananalog-to-digital (A/D) converter. A microprocessor receives as inputthe digitised output of the a/d converter.

[0006] The above circuit operates by receiving and integrating a signalfrom the photo diode and then resetting the integrator. The circuit thenfilters out the higher frequencies in the integrated signal, andconverts the analog filtered integrated signal to digital samples.Finally, the circuit calculates an integration slope for the photo diodesignal by fitting a curve to the digital samples. With the calculatedslopes, the circuit is better able to determine the original noiselesssignal from the photo diode. The circuit takes many readings perintegration period (which is of fixed predetermined length) and usessophisticated curve-calculation methods, such as, for example,least-squares curve fitting, to generate the per-period calculatedslopes.

[0007] Disadvantages of the above circuit are that, for high lightintensities, the signal is saturated before the predeterminedintegration time is over and the detector skips the signal aftersaturation until the next reset. On the other hand, for low lightintensities, the reset may occur more frequently than necessary so thatthe whole dynamic range of the AND converter is not used. Furthermore,every reset is a disturbance which needs valuable measurement time tosettle until the system is stable again (This may take as much as 10% ofthe time).

[0008] It is therefore an object of the present invention to provide amethod and apparatus for measuring a low power signal, for example froma photo diode, which overcomes, or at least reduces the disadvantages ofthe known method described above.

BRIEF SUMMARY OF THE INVENTION

[0009] Accordingly, in a first aspect, the present invention provides amethod of measuring a low power signal, comprising the steps of:

[0010] receiving a low power signal from a signal source;

[0011] integrating the received low power signal over controllableintegration periods to provide an integration signal;

[0012] sampling the integration signal at a frequency substantiallyhigher than a frequency of the integration periods to provide digitalsamples of the integration signal;

[0013] determining differences between digital samples to provide astream of delta values; and

[0014] filtering the stream of delta values to provide a filtered signalsubstantially matching the received low power signal.

[0015] In a preferred embodiment of the invention, the method furthercomprises the step of interpolating the delta values between integrationperiods so that the stream of delta values is continuous.

[0016] Preferably, the digital samples are compared to a predeterminedvalue and the integration period is reset if a digital sample has avalue which is not within the predetermined value.

[0017] In a second aspect, the invention provides an apparatus formeasuring a low power signal, comprising:

[0018] an input terminal for receiving a low power signal from a signalsource;

[0019] an integrator coupled to the input terminal and having an outputfor providing an integration signal formed by integrating the receivedlow power signal over controllable integration periods;

[0020] a digitiser coupled to an output of the integrator for samplingthe integration signal at a frequency substantially higher than afrequency of the integration periods to provide digital samples of theintegration signal at an output;

[0021] a processing means having an input coupled to the output of thedigitiser for determining differences between digital samples to providea stream of delta values at an output; and

[0022] a filter having an input coupled to the output of the comparatorfor filtering the stream of delta values to provide a filtered signalsubstantially matching the received low power signal at an output.

[0023] In a preferred embodiment of the invention, the processing meansincludes interpolation means for interpolating the delta values betweenintegration periods so that the stream of delta values is continuous.

[0024] Preferably, processing means includes comparison means forcomparing the digital samples to a predetermined value and for providinga reset signal to the integrator for resetting the integration period ifa digital sample has a value which is not within the predeterminedvalue.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] An embodiment of the present invention will now be described, byway of example, with reference to the accompanying drawings, of which:

[0026]FIG. 1 is a schematic drawing of a known circuit for measuring alow power signal;

[0027]FIG. 2 is a schematic drawing of an apparatus for measuring a lowpower signal according to a first embodiment of the invention;

[0028]FIG. 3 shows a set of schematic signal graphs for the circuit ofFIG. 1;

[0029]FIG. 4 shows a set of schematic signal graphs for the apparatus ofFIG. 2;

[0030]FIG. 5 shows a set of schematic signal graphs for the apparatus ofFIG. 2 with a different form of light intensity distribution to that ofFIG. 4; and

[0031]FIG. 6 shows a schematic flow chart of the operation of theapparatus of FIG. 2.

DETAILED DESCRIPTION OF THE DRAWINGS

[0032] Thus, FIG. 1 shows a known circuit 1 for measuring a low powersignal from a photodiode 2 when light of relatively low intensity(indicated by arrow 4) is incident upon the photodiode 2. The photodiode2 is coupled between a negative input 5 and a positive input 6 of anoperational amplifier 7. A capacitor 8 is coupled in a feedback pathbetween an output 9 of the operational amplifier 7 and its negativeinput 5. A field effect transistor (FET) 10 has its source electrodecoupled to the output 9 of the operational amplifier 7 and its drainelectrode coupled to the negative input 5 of the operational amplifier7, with its gate electrode serving to receive a reset signal to resetthe operational amplifier 7.

[0033] The output 9 of the operational amplifier 7 is coupled to aninput of a low-pass filter 11, whose output is, in turn, coupled to aninput of an analog-to-digital converter (A/D) 12. An output of the A/Dconverter 12 is coupled to an input of a microprocessor 13, whose outputprovides an indication of the measured signal, and hence of the lightincident on the photo diode 2.

[0034] The operational amplifier 7 receives and integrates the signalfrom the photodiode 2 over an integration period set by a reset signalreceived by the FET 10. The reset signal has a predetermined frequencyso that the integration periods are constant. The low-pass filter 11then filters out the higher frequencies in the integrated signal and theA/D converter 12 digitises the filtered integrated signal. Finally, themicroprocessor 13 calculates the integration slope for the photo diodesignal by fitting a curve to the digitised samples, for example using aleast-squares fit algorithm.

[0035] In operation, and referring now to FIG. 3, the graph of FIG. 3(a)shows a plot of an output signal 30 of the photo diode, which representsthe light intensity incident on the photo diode over a period of time.In this case, there is a background light level 31, which suddenlyincreases to a high level 32 when light is incident on the photo diodeand then drops back down to the background level when the light is nolonger incident on the photo diode. The operational amplifier 7 receivesand integrates the output signal from the photodiode 2 over anintegration period set by a reset signal received by the FET 10. As canbe seen in FIG. 3(b), the operational amplifier provides an integratedoutput signal 33 which includes a short reset period. This takes placeby charging the capacitor 8 to an initial charged level, which is theupper level 34 shown in FIG. 3(b). When no light is incident on thephoto diode, the capacitor slowly discharges through the operationalamplifier, which is shown as shallow slope 35, until the reset signal isreceived by the FET and the capacitor is recharged back to the initialcharged level 34. When the output signal from the photo diode is at thehigh level 32, the capacitor discharges more quickly through theoperational amplifier so that the slope 36 is steeper. As before, whenthe reset signal is received by the FET, the capacitor is recharged backto the initial charged level 34. The A/D converter 12 samples theintegrated signal at a frequency rate substantially higher than theintegration period frequency and provides a stream of these samples tothe microprocessor 13.

[0036] The samples for an integration period are stored and then a slopethat best fits the samples is calculated during the reset periods. Thisis shown in FIG. 3(c), where the calculated slopes are indicated bycrosses. In this case, while there is only background light incident onthe photo diode, the shallow slopes 35 of the integrated signal areconstant, as shown by crosses 37. When the incident light reaches thehigh level 32 during an integration period, as shown in FIG. 3(b), theslope changes from shallow to steep during the period, so that the bestfit slope for the period is an average of the two, as shown by cross 38in FIG. 3(c). When the incident light is at the high level 32 for thewhole of an integration period, the calculated slope for the period hasa high value, as shown by cross 39 in FIG. 3(c). It will be apparentthat timing and rate of change information is lost for the time whenlight incident on the photo diode changes.

[0037] As mentioned above, in the above circuit the signal is saturatedbefore the predetermined integration time is over for high lightintensities and the detector skips the signal after saturation until thenext reset. On the other hand, for low light intensities, the reset mayoccur more frequently than necessary so that the whole dynamic range ofthe A/D converter is not used. Furthermore, every reset is a disturbancewhich needs valuable measurement time to settle until the system isstable again (this may take as much as 10% of the time).

[0038]FIG. 2 shows an apparatus 20 according to a preferred embodimentof the present invention. In the drawing, the same elements as shown inFIG. 1 are given the same reference numerals. More particularly, lightof relatively low intensity (indicated by arrow 4) is incident upon thephotodiode 2. The photodiode 2 is coupled between the negative input 5and the positive input 6 of the operational amplifier 7. Capacitor 8 iscoupled in a feedback path between output 9 of the operational amplifier7 and its negative input 5. Field effect transistor (FET) 10 has itssource electrode coupled to the output 9 of the operational amplifier 7and its drain electrode coupled to the negative input 5 of theoperational amplifier 7, with its gate electrode serving to receive areset signal to reset the operational amplifier 7.

[0039] However, according to the present embodiment of the invention,the output 9 of the operational amplifier 7 is coupled to an input of ananalog-to-digital (A/D) converter 21. An output of the A/D converter 21is coupled to an input of a microprocessor 22, whose output is coupledto an input of a filter 23. A second output of the microprocessor 22 iscoupled to the gate electrode of FET 10 to provide the reset signal tothe FET 10.

[0040] In operation, and referring now to FIG. 4, the graphs of FIGS.4(a) and 4(b) are identical to those of FIGS. 3(a) and 3(b) and show theoutput signal 30 of the photo diode, which represents the lightintensity incident on the photo diode over a period of time with abackground light level 31 and a high level 32 as well as the integratedoutput signal 33. As before, the A/D converter 21 samples the integratedsignal at a frequency rate substantially higher than the integrationperiod frequency and provides a stream of these samples to themicroprocessor 22.

[0041] However, according to the present embodiment of the invention,instead of storing the samples for a complete integration period andthen calculating a best-fit curve (slope) to the samples, in thisembodiment of the invention, delta values are calculated between eachadjacent sample. A delta value is the difference between one sample andthe next. A plot of the delta values is shown in FIG. 4(c), where, ascan be seen, for each of the slopes 35 and 36, there is a differentdelta value 40 and 41, respectively. It will be appreciated that thedelta values 40 and 41 are each constant because slopes 35 and 36 areconstant slopes, so that adjacent samples of the slopes have a constantdifference.

[0042] In order to provide a continuous stream of data samples to thefilter 23, delta values are interpolated for the reset periods, shown asgaps in the delta value graph of FIG. 4(c). The interpolated delta valueplot 42 is shown in FIG. 4(d) where the gaps are filled in withinterpolated values calculated by the microprocessor 22 based on anysuitable interpolation algorithm. In the present case a simple linearinterpolation scheme is used. Such an estimation is generally acceptableif the number of estimated points is considerably lower (<10%) than thenumber of measured points. The continuous stream of data samples frommicroprocessor 22 is then passed to the filter 23, which can be aweighted filter that matches the form of the signal, for example aSavitszki-Golay filter can be used where the signal has Gaussian peaks.The output of the filter 23 is shown in FIG. 4(e), where, as can beseen, the signal is a good representation of the original photo diodeoutput signal 30.

[0043] Although the above example shows the integration period as aconstant predetermined period, with the reset signal being applied at aconstant frequency, as mentioned above, resetting the apparatus, evenwhen the integrator has not reached saturation, simply disturbs thesystem unnecessarily.

[0044] Therefore, according to the preferred embodiment of theapparatus, and as illustrated in the flow chart 60 of FIG. 6, theapparatus first receives the optical light signal at the photo diode andconverts it (step 61) to an electrical current signal. The currentsignal is then integrated (step 62) the integrated signal is sampled bythe A/D converter at a much higher frequency than the integration periodto provide a stream of digital data samples (step 63). Themicroprocessor 22 then compares the samples from the A/D converter 21 toa predetermined value, which is stored in a memory (not shown) to whichthe microprocessor is coupled and generates the reset signal applied tothe gate electrode of FET 10 when a sample is found to be at or higherthan the predetermined value (step 64). In this way, the apparatus isnot reset until the integrator approaches saturation so that, firstly,the apparatus is not disturbed until necessary, and, secondly, at highlight levels, the integration periods are short and the signal is “lost”only for the reset period itself, rather than for all the remainingintegration period after the integrator has reached saturation, as inthe prior art circuit with fixed integration periods.

[0045] The microprocessor 22 also calculates the differences betweenadjacent samples to produce delta values during the integration periodsand also interpolates the delta values for the reset periods to producea continuous stream of delta values (step 65). The continuous stream ofdelta values is then filtered by a Savitszki-Golay filter to produce areconstruction of the original signal (step 66).

[0046] This can be seen in FIG. 5, FIG. 5(a) is a graph showing anoutput signal 50 of the photo diode, with a background light level 51, amedium level 52, and a high level 53. FIG. 5(b) shows the integratedsignal 54, with dynamically set reset periods. As shown, while onlybackground light is present, the integration period is allowed tocontinue, so that the integrated signal continues with a long shallowslope 55, until the operational amplifier is nearly saturated before themicroprocessor generates the reset signal and the capacitor isrecharged. In this case, the reset is coincident with an increase in thelight level to the medium level. As can be seen, following the resetperiod during which the integrated signal is constant at the chargedlevel 56, the integrated signal then falls with a steeper slope 57 andis then reset for a further period during which it again falls with thesame slope indicating that the incident light remains at the mediumlevel 52. Finally, as the light level increase to the high level 53, theslope of the integration signal increases to a very steep slope 58, withcorrespondingly shorter integration periods.

[0047] The delta values between the digitised samples of the integrationsignal 54 are shown in FIG. 5(c), where delta values 58, 59 and 60corresponding to integration signal slopes 55, 56 and 57, respectively.As before, the gaps in the delta values due to the reset periods arethen interpolated by the microprocessor to provide a continuous streamof data samples, shown as the interpolated signal 61 in FIG. 5(d), whichare then filtered by the filter to provide a filtered representation 62of the original signal 50.

[0048] Thus, the embodiment of the invention described above provides adynamic reset which depends only on signal level and not on a fixedtime, and achieving a continuous stream of equidistant data byinterpolating the delta values for the reset periods so that a weightedfilter can be used. The advantages of a dynamic reset are that at highlight levels the time intervals between the resets are short and thesignal is lost only during the reset period itself, whereas at low lightlevels the reset occurs only if the integrator is about to go intosaturation and this means that there is factor of about 20 fewer resetcycles at typical low light intensities.

[0049] By having an equidistant continuous stream of data under alllight conditions, any suitable filter can be used and a fixed timeperiod for the measurement can be avoided. Thus, the filter firmware canbe optimised for a wide range of frequency behaviour of the signalwithout changing the hardware. Furthermore, by sampling during the wholeslope, instead of resetting after every point as in a standard A/Dconverter, rounding errors introduced by digitising the signal arecompensated with the following values because the integrating capacitoraccumulates charge without rounding errors. Finally, the output datarate of the system becomes independent of the reset frequency so that athigh light levels the system is not “blind” for a considerablepercentage of the cycle time.

[0050] Whilst only one particular embodiment of the invention has beendescribed above, it will be appreciated that a person skilled in the artcan make modifications and improvements without departing from the scopeof the present invention.

1. A method of measuring a low power signal, comprising the steps of:receiving (61) a low power signal from a signal source; integrating (62)the received low power signal over controllable integration periods toprovide an integration signal; sampling (63) the integration signal at afrequency substantially higher than a frequency of the integrationperiods to provide digital samples of the integration signal;determining (65) differences between digital samples to provide a streamof delta values; and filtering (66) the stream of delta values toprovide a filtered signal substantially matching the received low powersignal.
 2. A method of measuring a low power signal according to claim1, further comprising the step of interpolating (65) the delta valuesbetween integration periods so that the stream of delta values iscontinuous.
 3. A method of measuring a low power signal according toeither claim 1 or claim 2, further comprising the step of comparing (64)the digital samples to a predetermined value and resetting theintegration period if a digital sample has a value which is not withinthe predetermined value.
 4. An apparatus for measuring a low powersignal, comprising: an input terminal (5) for receiving a low powersignal from a signal source (2); an integrator (7, 8, 10) coupled to theinput terminal (5) and having an output (9) for providing an integrationsignal formed by integrating the received low power signal overcontrollable integration periods; a digitiser (21) coupled to the output(9) of the integrator (7, 8, 10) for sampling the integration signal ata frequency substantially higher than a frequency of the integrationperiods to provide digital samples of the integration signal at anoutput; a processing means (22) having an input coupled to the output ofthe digitiser for determining differences between digital samples toprovide a stream of delta values at an output; and a filter (23) havingan input coupled to the output of the processing means (22) forfiltering the stream of delta values to provide a filtered signalsubstantially matching the received low power signal at an output.
 5. Anapparatus for measuring a low power signal according to claim 4, whereinthe processing means (22) includes interpolation means for interpolatingthe delta values between integration periods so that the stream of deltavalues is continuous.
 6. An apparatus for measuring a low power signalaccording to either claim 4 or claim 5, wherein the integrator (7, 8,10) comprises an operational amplifier (7) having a first input coupledto the first terminal (5) and an output (9), a capacitor (8) coupledbetween the first input and the output (9) of the operational amplifier(7), and a transistor (10) having current electrodes coupled between thefirst input and the output (9) of the operational amplifier (7) and acontrol electrode for receiving a reset signal for controlling theintegration periods.
 7. An apparatus for measuring a low power signalaccording to claim 6, wherein the transistor (10) is a Field EffectTransistor.
 8. An apparatus for measuring a low power signal accordingto either claim 6 or claim 7, wherein the processing means (22) includescomparison means for comparing the digital samples to a predeterminedvalue and for providing the reset signal for resetting the integrationperiod if a digital sample has a value which is not within thepredetermined value.
 9. An apparatus for measuring a low power signalaccording to any one of claims 4 to 8, wherein the digitiser (21)comprises an analog-to-digital converter.
 10. An apparatus for measuringa low power signal according to any one of claims 4 to 9, wherein thefilter (23) is matched to the form of the low power signal.
 11. Anapparatus for measuring a low power signal according to claim 10,wherein the filter (23) is a Savitszki-Golay filter.